The present invention relates to analog-to-digital converters, particularly to real-time failure detection systems for such converters.
Analog-to-digital conversion is the process of converting an analog data signal, which is most commonly represented as voltage, into a digital format. Determining a digital value which represents a particular analog input is known as xe2x80x9cquantizationxe2x80x9d. Successive approximation, serial, delta-sigma or oversampling, parallel, and pipelined are some of the many different analog to digital conversion architectures which currently exist.
Analog-to-digital converters (ADCs) are used increasingly in a wide range of applications. ADCs enable many systems to implement real-time processing of analog data. Such data capture and processing systems usually include sensors for collection of analog information and digital signal processors (DSPs) or microprocessors for processing of the data. Since the sensors deliver analog voltages whereas the processors compute digital values, an ADC, either as an embedded function or as a stand-alone chip, is needed to convert the data.
The ADCs in such real-time processing systems are expected to provide reliable data to the processor which acts on the information. Reliable data is required to ensure a reliable system response. This dependence is especially true of systems which are designed to perform safety related tasks. Several examples of these tasks can be found in the automotive industry. For example, engine and transmission control tasks, such as engine knock detection, as well as anti-lock braking systems (ABS) have a direct relationship to the safety of a vehicle. In such systems, reliability is paramount. Consequently, an ADC must provide reliable data to the processor to aid in a reliable system response.
In general, modern ADCs have multiple connections, both internally and externally. One ADC can be used to provide digital output for many (16, 32, or more) analog input connections (or xe2x80x9cpinsxe2x80x9d). Failures in such ADCs can appear anywhere. For example, a high voltage stress to a pin while an application is running can create an open or short circuit condition. By computing an incorrect value, and hence, wrong data, the digital processor can enter a critical and dangerous situation. This potential is especially true of safety critical applications such as those in the automobile industry.
FMEA
Mary automakers have adopted the failure mode and effect analysis (FMEA) discipline. The goal of FMEA is to identify and minimize the effects of potential problems in product or process designs. The fundamental questions answered under the discipline are:
1) How might the product fail?
2) What might be the cause and effect of such a failure? and
3) What controls are in place to detect such a failure?
Thus, FMEA seeks to eliminate costly failures in the manufacture of a product by ensuring critical issues are addressed before expensive commitments are made.
Several methods currently exist to self-test and detect the failure of analog-to-digital converters. The digital communication, from an ADC to a processor, is checked through bus protocols and/or software algorithms. However, the analog signal itself could be corrupt. For example, the analog voltage to be converted can be issued from a xe2x80x9cbad sourcexe2x80x9d. Bad source failures include situations such as open circuits or circuits shorted to ground or to a power supply. Such bad source failures can leave the ADC input pin(s) in a floating potential. These failures will not be detected by the testing of the ADC core (the converter circuitry itself) or by the testing of digital communications between the ADC core and a processor. To be efficient, the failure detection system must include a check from the pin connection to the digital communications (ADC to processor). Additionally, the pin connections must be tested all along the application.
A majority of the real-time failure detection in ADCs is carried out through the use of a small number of solutions. The most common solution employs a redundant ADC. The two ADCs are used to perform parallel conversions of a single analog voltage connected to one single-ended input of each ADC. The results of the parallel conversions are compared by the processor. If the results match, within limits, then no failure is detected. However, failure of the results to match, within limits, indicates that a failure has occurred. This functional redundance solution permits detection of a failure on one of the two connections. However, it requires duplicate ADC core hardware, increasing expense. Another problem with this redundancy solution is that it offers no indication of the type of failure that has occurred e.g., pin open, pin short, etc.
Another frequently implemented solution is the connection of a single input voltage to two different channels of a single ADC core. Use of this solution allows for the detection of a failure in the ADC due to a pin problem. Such a failure can be due to an open or a shorted pin. However, this solution, by itself, precludes the recognition of other failures. These other failures can include internal connection problems in the ADC module. Such problems can occur at the digital interface with the ADC core. Another disadvantage of this solution is increased production expense. The redundancy requirement of the additional channel impairs the cost effectiveness of this solution. Redundancy also results in increased conversion time. Conversion time for this solution is doubled since conversion are performed sequentially.
Both of the current solutions based on redundancy require either hardware or software control (via a microprocessor). Added control requirements results in hardware logic or code overhead (requiring additional memory size). Either method of control implementation requires an increased system size and hence, an increased cost.
Another self-test solution used in ADCs, such as the TLC2543 by Texas Instruments, is the use of three reference voltages. In such solutions, an additional known voltage source is provided to the ADC. This additional voltage source is provided on a dedicated input. Such a test can be used to check the ADC core and is often used as a production test to validate ADC functionality.
The present application discloses a real-time self failure detection mechanism for analog-to-digital converters. The output line of an analog signal to be sampled is connected to the input of an ADC along with a reference test voltage that is either high or low. In the presently preferred embodiment, analog sensors, for example, those which produce engine control data, provide signals within various operational ranges. During the sampling phase of an analog-to-digital conversion, a high test voltage will tend to drive the sampled value above the operational range of the analog signal. A low test voltage will drive the sampled value below the operational range of the analog signal.
After a programmable sample time has elapsed, the test voltage is disconnected from the input line, leaving only the analog output line connected to the ADC input. After a second programmable sample time, the signal at the ADC input is converted to a digital value by the ADC core, The result, a digital value, is analyzed to determine if a failure has occurred. If the result is outside the operational range of the particular sensor, a failure is indicated.
In one class of embodiments, the type of failure that has occurred can be determined by switching the test voltage. That is, if the previous test voltage was high, the test is performed again with a low test voltage, or vice-versa. If the second result remains relatively unchanged from the first, the failure indicated is a short of the pin to ground or the power supply, regardless of test voltage. If the result approximates the test voltage after each switch, that is, when the test voltage is high the result is above the operational range of the analog signal, or vice versa, the failure indicated is an open pin. An open pin failure indicates that no analog signal is being received at the ADC core.
An advantage of the present disclosure is that it is easy to implement and compatible with any CMOS standard process. The disclosed method relies only on analog switches and resistors that do not require a high degree of accuracy.